{"schema_version": 3, "recorded_at": "2026-07-30T08:07:36.334607+00:00", "device": {"name": "NVIDIA H200 NVL", "compute_capability": "9.0", "concurrent_processes": [], "note": null, "co_tenancy_visibility": "namespace-limited: measured from inside the Aerial container, so host processes are INVISIBLE here. An empty list does NOT mean the GPU was idle \u2014 verify from the host with nvidia-smi before claiming a clean run."}, "harness": "pyaerial LdpcDecoder + cudaEvent per call", "measures": "GPU elapsed time of ONE cuPHY LDPC decode over 81 code blocks, timed on the decoder's own CUDA stream.", "is_a_full_slot": false, "scope_warning": "LDPC decode only. A 5G slot also carries control channels, DMRS and the rest of the PUSCH/PDSCH chain, so a miss counted here is a miss BY THE DECODER ALONE and is a LOWER BOUND on real slot overrun.", "series_note": "cuphy_decode is cuPHY's LDPC decode. pyaerial_decode is the same work wrapped in pyAerial's public decode(), which re-copies the LLR block and the output on every call. Quote cuphy_decode for PHY latency; the difference is Python-binding overhead the real L1 does not pay.", "config": {"base_graph": 1, "lifting_size": 384, "info_bits_per_cb": 8448, "code_blocks": 81, "code_block_size_K": 8448, "llr_buffer_rows_per_cb": 26112, "tb_rate_match_length": 1351680, "code_rate": 0.5, "mod_order": 8, "num_layers": 4, "redundancy_version": 0, "tb_size_bits": 675840, "ldpc_iterations": 10, "throughput_mode": true, "input_built_by": "aerial LdpcDeRateMatch (shape derived, not hard-coded)"}, "llr_mode": "random", "llr_mode_note": "random: Gaussian LLRs, no valid codeword, early termination never fires -> full iteration count -> WORST case. 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